Ridgeback (8877) SIT CPLD Code Update
12/11/06
IO CPLD Revision: 0x23
CPU CPLD Revision: 0x23
Power CPLD Revision: 0x23
CONTENTS
---------
1.0 Overview
2.0 Change History
3.0 Update Instructions
4.0 Hardware Checkpoints
5.0 Jumpers and LED's
6.0 Unattended Mode
1.0 Overview
--------------
1.1 Dependencies
Hardware:
IO Planar: pass 2 or later, HT-2100 A0 or A2 (i.e. non-A1)
CPU Card: n/a
BIOS: n/a
BMC: n/a
1.2 Defects Addressed
n/a
1.3 Changes In This Release
- fixed incorrect reporting of certain CPU Vcore VRD
slave faults as Vddio faults due to Vddio VRDs losing
voltage too quickly
- preset 0x4cc debug register to 0x00 prior to BMC
generated reset event for better fault isolation
2.0 Change History
--------------------
0x22 - initiate sync flood via HT1000 upon PCI-X PERR
0x21 - removed PCI/E/X resets on sync flood to aid in error
reporting; J58 now has opposite effect - will force
PCI/E/X resets on sync flood
- PS PWRGD I2C bits 0xb0[5:4] now qualified by power
supply presence; will be '0' if power supply is absent
- simulate "power button" pulse to BMC if SIO initiates
power on with ONCTL# by itself (e.g. RTC wake)
- setting 0x4c5[4]=0 will now generate SMI (via HT1000
GEVENT0) ~100ms after writing bit
- value of port 80 at the time of a reset button event or
BMC generated reset event (including after sync flood)
will now be captured in 0x4cc; value will remain until
an AC power cycle or 0x4cc[0] is reset to '0'
- setting 0x4c9[7]=0 will now blink CPLD debug LEDs
for mfg test
0x20 - REMOVED HT2100 A1 bug work arounds
- REMOVED filter for 240VA fault generated by over spec
SDV Delta fans
- changed KMI_RESET_CPLD_N to be driven by power good
instead of reset
0x17 - 5708 ethernet voltages turn on sooner allowing
initialization to complete before BMC attempts to
communicate via I2C
0x16 - HT2100 A1 bug work around: force reboot if checkpoint
'00' hang (no first BIOS checkpoint)
- 0x4c4[7] now accepts writes; BIOS can disable WOL bypass
by writing 0x4c4[7]=0, similar to installing jumper J63
- widened pulse on NIO_PME_L and SLOT_GPE_L to overcome SIO's
internal debounce circuit which is enabled by default
0x15 - HT2100 A1 bug work arounds: force reboot if checkpoint
'6.6' hang (no first fetch) or BIOS checkpoint '42' hang
- J58 now blocks reset of PCI devices upon fatal error
for debug purposes
- FLASH_XA2x signals now driven low when in standby to
reduce leakage current
0x14 - force PCI-X bus to 100MHz unless slot 5 is empty and
slot 6 is populated; previously single card in either
slot would yield 133MHz
- implemented CPU_BMC_DBRDY change that was left out of 0x13
- no longer generate SMIs on ALERT# from CPLD
- allow multiple 'A:x' on checkpoint display
- I2C 0x60[3:2] now clear-on-read to allow multiple
ALERT# events
- changed polarity of 0x4c3[6] for backwards compatibility
- on sync flood, checkpoint display will now alternate
between 'F:x' and the last BIOS checkpoint
0x13 - no longer removing power from ethernet chips on DC off
to reload defaults; solves BMC ethernet connection issues
- filtered 240VA fault on 12V radials with fans to mask
current Delta fan over spec inrush current
- reading IO I2C register 0x6c now returns BIOS port 80;
writes still BMC power on prevent checkpoints
0x12 - changed CPU Vtt and Vddio sequencing to meet 1.1V
gap specification on power up/down
- changed post-sync flood error handling to new scheme
- increased power-on delay after AC power failure
to allow BMC time to initialize
- added J57 to force HDT path to HDT connectors rather
than the BMC for debug after sync flood
- preset BMC system power-on prevent checkpoint to '62'
instead of '00'
- returned power supply fan control to BMC
0x11 Initial SDV Release
3.0 Update Instructions
-----------------------------------------
***** AFTER UPDATE, AC POWER CORD(S) MUST BE *****
***** UNPLUGGED FOR 30 SECONDS *****
1) Create bootable diskette from zycpld23.img file or
bootable CD from zycpld23.iso file.
2) Insert media into system to be updated and boot
from that media.
3) Confirm CPLD update at prompt. Upon successful
completion, remove AC power for 30 seconds.
Code updates will not take effect until AC power
is cycled.
Note: *.pof files are included on media in case
programming via cable becomes necessary.
***** AFTER UPDATE, AC POWER CORD(S) MUST BE *****
***** UNPLUGGED FOR 30 SECONDS *****
4.0 Hardware Checkpoints
--------------------------
Ridgeback Hardware Checkpoints
1.x power faults
1.0 1_8v_stby
1.1 epow
1.2 sys_chan_good
1.3 backplane_pgood
1.4 cpu_vrm_sfault_n
1.5 12v_a
1.6 12v_b
1.7 12v_c
1.8 12v_d
1.9 12v_e
1.a 12v_f
1.b 12v_g
1.c 12v_h
1.d 12v_j
1.e 12v_k
3.x io vrm faults
3.1 1_2v_enet
3.2 5v_vrm
3.3 3_3v_vrm
3.4 2_5v_video
3.5 1_8v_video
3.6 2_1v_sas
3.7 1_8v_sas
3.8 1_4v_sas
3.9 2_5v_bcm
3.a 1_2v_2100
3.b 1_2v_1000
3.c io_pwrgood
4.x & 5.x cpu vrm faults & status
4.0 cpu4_vtt
4.1 cpu3_vtt
4.2 cpu2_vtt
4.3 cpu1_vtt
4.4 cpu4_vddio
4.5 cpu3_vddio
4.6 cpu2_vddio
4.7 cpu1_vddio
4.8 cpu4_vdda
4.9 cpu3_vdda
4.a cpu2_vdda
4.b cpu1_vdda
4.c cpu4_vcore
4.d cpu3_vcore
4.e cpu2_vcore
4.f cpu1_vcore
5.0 vldt
5.1 cpu_pwrgood
5.2 cpu4_thermtrip
5.3 cpu3_thermtrip
5.4 cpu2_thermtrip
5.5 cpu1_thermtrip
5.6 cpu_pop_err
6.x system control
6.1 on_ctl_n
6.2 bmc_pwron
6.3 pwrok
6.4 ht1000_reset_in_n
6.5 pci_reset
6.6 lpc_check
7.x slot vaux faults
7.1 s1_vaux
7.2 s2_vaux
7.3 s3_vaux
7.4 s4_vaux
7.5 s5_vaux
7.6 s6_vaux
Ridgeback System Error Checkpoints
F:0 fatal error/sync flood detected by HT2100-A
F:1 fatal error/sync flood detected by HT2100-B
A:0 non-fatal error (ALERT#) detected by HT2100-A
A:1 non-fatal error (ALERT#) detected by HT2100-B
S:1 SERR on PCI-X bus
P:1 PERR on PCI-X bus
S:0 SERR from ATI graphics chip
5.0 Jumpers and LED's
-----------------------
5.1 Jumpers
J56 make all system resets "warm"
J57 force HDT path to HDT connectors on sync flood (not BMC)
J58 force PCI resets on fatal error
J59 external system reset input
5.2 LED's
CR47 "power backplane" power good
CR48 global VRD or THERMTRIP fault
CR49 n/a
CR50 HT2100-A ALERT
CR51 HT2100-A FATAL
5.0 Unattended Mode
---------------------
To use the diskette in unattended mode, change the
following line in autoexec.bat
cpldprog.exe ridge_xx.jbc
to
cpldprog.exe -u ridge_xx.jbc